The present invention concerns the technical field of receivers able to demodulate electric signals and, more precisely, direct conversion receivers for frequency-shift keying (FSK) modulated signals.
With reference to FIG. 1 of the present description, European Patent No. 0,405,676 discloses a receiver 1 including an antenna 2, direct conversion means 3, two limiting amplifiers 28 and 30, demodulation means 5 and a bistable memory 6 connected in series.
Antenna 2 receives a frequency-shift modulated signal S and supplies this signal. In the present description, it will be recalled that FSK modulation is a modulation allowing the supply of a signal at a frequency equal to a value fp+xcex94f1 to transmit one of the two states of the signal, and at another value fpxe2x88x92xcex94f1 to transmit the other state, the references fp and xcex94f1 respectively designating a nominal carrier frequency and a frequency shift. For a data rate equal to 512 bits/s, the frequencies fp and xcex94f1 have the respective values 400 MHz and 4.5 kHz.
Conversion means 3 includes two mixers 12 and 14, a local oscillator 16, a 90xc2x0 phase shifter and two low-pass filters 20 and 22. Oscillator 16 provides a frequency fL which is ideally equal to carrier frequency fp. Mixer 12 (14 respectively) includes a first input terminal for receiving signal S, a second input terminal for receiving frequency fL, and an output terminal connected to filter 20 (22 respectively). Moreover, mixer 14 is connected to oscillator 16 via phase shifter 18. As a result of this arrangement, if the frequency of signal S equals fp+xcex94f1, the frequencies provided by mixers 12 and 14 respectively equal +xcex94f1 and +xcex94f1xe2x88x92xcfx80/2 and, if the frequency of signal S equals fpxe2x88x92xcex94f1, the frequencies provided by mixers 12 and 14 respectively equal xe2x88x92xcex94f1 and xe2x88x92xcex94f1xe2x88x92xcfx80/2. Filter 20 (22 respectively) can receive the frequency provided by mixer 12 (14 respectively) and, in response, provide a signal I (respectively a signal Q). It will be recalled that signals I and Q represent the real and imaginary parts of a complex signal having a negative frequency (in this case xe2x88x92xcex94f1) or a positive frequency (in this case +xcex94f1). FIG. 2 of the present description shows two timing charts 24 and 26 illustrating signals I and Q, respectively. As FIG. 2 shows, signals I and Q are analog signals having substantially sinusoidal wave shapes in phase quadrature. The presence of a phase change of signal Q will be noted, as illustrated by timing chart 26.
With reference once more to FIG. 1, limiting amplifiers 28 and 30 can receive signals I and Q and, in response, provide signals I1 and Q1 respectively. It will be recalled that a limiting amplifier receives an input signal, and provides an output signal whose amplitude does not increase in practice beyond a determined amplitude of the input signal. FIG. 3A of the present description shows two timing charts 32 and 34 illustrating signals I1 and Q1 respectively. As FIG. 3A shows, signals I1 and Q1 are digital signals having wave shapes which are offset with respect to each other and rectangular, the amplitudes of signals I1 and Q1 equalling xe2x88x921 or +1.
FIG. 3B shows a curve 80 illustrating the relationship between the instantaneous values I1(t) and Q1(t) of signals I1 and Q1 at an instant t. As FIG. 3B shows, curve 80 has a rectangular shape wherein the peaks are formed by four points A to D. It will be noted that a temporal evolution of these signals translates into a path along this curve, so that, when signal Vout equals 0 (1 respectively), signals I1 and Q1 are represented in succession by points A, B, C, D, A . . . (respectively A, D, C, B, A . . . ), i.e. a path along the trigonometric direction (respectively the opposite direction to the trigonometric direction).
With reference once again to FIG. 1, demodulation means 5 include a differentiator circuit 40 (42 respectively), a multiplier 36 (38 respectively) and a subtractor 39 connected in series.
Multiplier 36 (38 respectively) includes a first input terminal for receiving signal Q1 (I1 respectively) and a second input terminal for receiving signal I1 (Q1 respectively), via differentiator circuit 40 (42 respectively). Multiplier 36 (38 respectively) is arranged for providing signal X1 (Y1 respectively). FIG. 4 of the present description shows two timing charts 44 and 46 illustrating signals X1 and Y1 respectively. As FIG. 4 shows, signal X1 contains first pulses, and signal Y1 contains second pulses offset with respect to the first pulses. Subtractor 39 includes a first input terminal for receiving signal X1 and a second input terminal for receiving signal Y1. Subtractor 39 is arranged to provide a signal X1-Y1 equal to the difference between signals X1 and Y1. FIG. 5 of the present description shows a timing chart 48 illustrating signal X1-Y1. As FIG. 5 shows, signal X1-Y1 contains the pulses resulting from the difference between signals X1 and Y1. It will be noted that, prior to the phase change of signal Q, signal X1-Y1 contains negative pulses and that this phase change causes positive pulses to be supplied.
Bistable memory 6 includes an input terminal for receiving signal X1-Y1, and an output terminal for providing a signal Vout in response. FIG. 6 of the present description shows a timing chart 50 illustrating signal Vout. As FIG. 6 shows, signal Vout is equal to a level  less than  less than 0 greater than  greater than  or to a level  less than  less than 1 greater than  greater than . It will be noted that, as soon as a positive pulse appears on signal X1-Y1, signal Vout switches from level  less than  less than 0 greater than  greater than  to level  less than  less than 1 greater than  greater than , and remains at this level, independently of the subsequent frequency difference between signals X1 and Y1.
The operation of receiver 1 will now be briefly described with reference to FIGS. 1 to 6 cited above.
Up to an instant t01, signals I1 and Q1 are periodic of period T, signal I1 being in advance of signal Q1, so that signal Vout equals 0. Signals I1 and Q1 are represented in succession by points A, B, C, D, A . . . Thus, at instant t01, signal Q1 becomes equal to 1. At an instant t1 subsequent to instant t01, and prior to instant t01+T/2, a new data item is present in signal Q1, so that the timing of signals I1 and Q1 is reversed after instant t01+T/2 (i.e. signals I1 and Q1 are represented in succession by points B, A, D, C, B . . . ). It will be noted that the switching of signal Vout occurs during the following switching of signal I1 to level xe2x80x9cxe2x88x921xe2x80x9d, i.e. at an instant t3. In other words, there is a time delay between the instant when the data is contained in signal Q (i.e. instant t1) and the instant when the data is contained in signal Vout (i.e. instant t3). It will also be noted that this time delay is comprised between T/2 and T, which requires a high xcex94f/D ratio, the reference xcex94f designating the frequency shift (equal in this case to Df1) and the reference D designating the bit rate. Thus one drawback of receiver 1 is that there is a high xcex94f/D ratio: one bit is typically provided every four periods.
In order to overcome this drawback, there exist in the state of the art FSK modulated signal receivers which perform demodulation directly from the analog signals I and Q provided by the conversion means.
With reference to FIG. 7 of the present description, U.S. Pat. No. 5,640,428 discloses a receiver 90 including an antenna 2, conversion means 3, demodulation means 92 and a low-pass filter 94. It will be noted that the elements in FIG. 7 which are similar to those described in relation to FIG. 1 have been designated by the same references. As FIG. 7 shows, demodulation means 92 include four mixers 96 to 99, two holding circuits 100 and 101 and three delay circuits 102 to 104. It will be noted that receiver 90 performs demodulation of a signal S received by antenna 2, by analog processing of such signal. However, this processing is achieved by digital processing elements (clock signals, flip-flops) in the same way as receiver 1 of FIG. 1.
Moreover, one drawback of receivers 1 and 90 is that demodulation means 5 and 92 contain multipliers which are components having a complex structure (in particular two input terminals), i.e. components which are difficult to manufacture.
One object of the present invention is to provide an FSK modulated signal receiver which overcomes the aforementioned drawbacks, in particular a receiver of this type which performs instantaneous demodulation on the basis of analog signals.
Another object of the present invention is to provide an FSK modulated signal receiver which performs demodulation of data received with a minimum xcex94f/D ratio (typically less than 1).
Another object of the present invention is to provide an FSK modulated signal receiver having demodulation means which do not include any multipliers.
Another object of the present invention is to provide an FSK modulated signal receiver which answers the criteria of rationality, compactness and cost, which are conventional in the semiconductor industry.
These objects, in addition to others, are achieved by the receiver according to claim 1.
One advantage of the complex filter of such a receiver is that it can be made by semiconductor components which are simple to manufacture, without forming multipliers or mixers with several inputs, like conventional receivers.
Another advantage of the filter of such a receiver is that it filters half of the noise originating from the modulated signal, which considerably reduces the influence of noise on the receiver output signal.